
PIC18F1230/1330
2009 Microchip Technology Inc.
DS39758D-page 103
REGISTER 11-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
R/W-1
U-0
R/W-1
U-0
R/W-1
U-0
OSCFIP
—
EEIP
—LVDIP
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
OSCFIP:
Oscillator Fail Interrupt Priority bit
1
= High priority
0
= Low priority
bit 6-5
Unimplemented:
Read as ‘0’
bit 4
EEIP:
Data EEPROM/Flash Write Operation Interrupt Priority bit
1
= High priority
0
= Low priority
bit 3
Unimplemented:
Read as ‘0’
bit 2
LVDIP:
Low-Voltage Detect Interrupt Priority bit
1
= High priority
0
= Low priority
bit 1-0
Unimplemented:
Read as ‘0’
REGISTER 11-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3
U-0
R/W-1
U-0
—
—PTIP
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented:
Read as ‘0’
bit 4
PTIP:
PWM Time Base Interrupt Priority bit
1
= High priority
0
= Low priority
bit 3-0
Unimplemented:
Read as ‘0’